Physical Design Engineer

Block level design from RTL-to-GDSII: synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff
Proficient with Cadence Implementation tool suite (Genus, Innovus)
Controllers for High Speed IO IP's
Structural implementation: datapaths, bus planning and routing
Experience with multi-power domain design
Solid scripting skills in tcl and python

Sintegra

06/01/2024

Austin,TX